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Minister Rajeev Chandrasekhar Launches Nationwide Roadshow on Digital India RISC-V Program

Union Minister of State for Skill Development & Entrepreneurship and Electronics & IT, Shri Rajeev Chandrasekhar, has launched a nationwide roadshow on Digital India RISC-V (DIR-V) Program, jointly organized by C-DAC, IEEE India Council, and MeitY, featuring global leaders in the RISC-V design area.

As part of the Digital India RISC-V (DIR-V) program announced by Minister Rajeev Chandrasekhar in 2022, successful tapeouts were carried out for – (a) 32-bit/ 64-bit SHAKTI Processors at 180nm (SCL foundry) and 22nm (Intel foundry) by IIT Madras, (b) 32-bit AJIT Processor at 180nm (SCL foundry) by IIT Bombay, and (c) 32-bit VEGA Processors at 130nm (Silterra foundry) and 64-bit VEGA Processors at 180nm (SCL Mohali) by C-DAC.

C-DAC has now created a series of ARIES Development Boards based on VEGA Processor Chip viz. ARIES Micro, ARIES V2, ARIES V3, ARIES IoT and ARIES DOT. These development kits are fully indigenous and ‘Made in India’ products targeted for learning, embedded system design, and IoT applications. The boards, built upon the RISC-V ISA-compliant VEGA Processor, come with easy-to-use hardware and software.

According to Minister Rajeev Chandrasekhar, this program is playing a pivotal role in realizing the vision laid by PM Modi of creating and adoption open-source technologies.

Shri Rajeev Chandrasekhar said, “Our prime focus is to enable the growth of the DIR-V ecosystem, aiming for India to emerge as a leading nation in innovating around the DIR-V family of chips and systems. This program will play a pivotal role in realizing Prime Minister Narendra Modi ji’s vision of creating and adopting open-source technologies. Start-ups, students, and entrepreneurs will play crucial roles in developing DIR-V-based chips and systems, ultimately contributing to India becoming a Semiconductor Nation,”

He also highlighted how this program will ensure DIR V-based chips and systems are integrated into various digital products we use daily. “In the last 50 years, computer processors have evolved with many ideas, eventually settling on one main design that everyone adopts. Now, our focus is on the DIR-V program, envisioning a future where DIR V-based chips and systems are integrated into various digital products we use daily. India has also embraced RISC-V in flagship government projects, witnessing growth in startup research and innovation around RISC-V. India hosts several startups working on RISC-V-based designs, which are also part of MeitY’s futureDESIGN initiative. For instance, Incore Semiconductors is developing configurable RISC-V processor cores, Mindgrove Technologies is working on fault-tolerant systems, and Morphing Machines is developing multi-core reconfigurable systems,” the Minister further added.

The DIR-V VEGA series of processors will be showcased at a roadshow for 1500 participants, covering theoretical and practical aspects such as development boards, SDK, and application development. Hands-on sessions will be conducted using Arduino-compatible ARIES development boards. Key global leaders, including Prof. Krste Asanovic, Calista Redmond, Balaji Baktha, and Prof. Kamakoti, will address the event.

The event is being held at 15 academic institutions across India, including Alliance University in Bangalore, Amrita University in Bangalore, Birla Institute of Technology and Science in Pilani, Chandigarh University in Punjab, Cochin University of Science and Technology in Kerala, Guru Tegh Bahadur Institute of Technology in Delhi, Indian Institute of Information Technology in Madhya Pradesh, KIET Group of Institutions in Ghaziabad, Koneru Lakshmaiah University in Andhra Pradesh, Mody University of Science and Technology in Rajasthan, Netaji Subhash Engineering College in West Bengal, PSG College of Technology in Tamil Nadu, Thakur College of Engineering and Technology in Maharashtra, and Vellore Institute of Technology in Tamil Nadu.

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Source: PIB

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